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Recent content by ramesh.balaram

  1. R

    help me in interconnecting two verilog modules

    if you have doubt regarding only inter-connection of module then this is how i can apply ...... module top_high; reg Tte_reg; reg clk_reg; reg resetn_reg; wire [35:0]out_wire; reg [8:0]E_reg; reg [8:0]A_reg; reg [8:0]B_reg; reg [8:0]C_reg; wire PA_wire,PB_wire,PC_wire...
  2. R

    [SOLVED] clarification in SPECMAN - E

    can any body tell me the difference b/w "it" and "me ".....???????? where to use exactly?????
  3. R

    [SOLVED] instantiating verilog module in vhdl

    how to use a xilinx unisim library component written in verilog, in a vhdl top level code how to perform the port mapping
  4. R

    [SOLVED] how to assign more I/O pins in fpga

    hai i am new to fpga board... i am using spartan 3e.. i have instantiated block ram by using unisim library... and i want to test the block ram by dumping into the fpga... problem is that my block ram has 9 bit address , 8 bit datainput,clk,rst,we, how can i connect to fpga io buffer...
  5. R

    Vlsi jobs for freshers..

    hi iam fresher...... b.tech 2009 and presentely completed "certification course in vlsi " at pune university......... is there any openings right now ..... please help me....
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