Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by rambus_ddr

  1. R

    [SOLVED] How to use PSS of Cadence Spectre ?

    Re: pss convergence it maybe need set a correct beat frequency for simulation, such as fclock/1.5
  2. R

    all pass filter realization

    Thanks, flatulent. I want to realize a rising phase vs frequency, so it need a positive pole, and negative zero. But in many paper and book, there are a negative pole and positive zero.
  3. R

    all pass filter realization

    I want to realize the Tranfer function (1+a*s)/(1-a*s), not(1-a*s)/(1+a*s). How can I use one opamp and RC to realize, please give your advice, thanks.
  4. R

    Where can download TSMC design kit for ADS ? Thx

    tsmc 13 download when i use this design kit to do simulation, it alway report the following error? can you give me some advice? thanks! Simulation / Synthesis Messages Error detected by hpeesofsim during netlist flattening. While evaluating expression `nch_rf.Tox': expression has...
  5. R

    hand calculate model problem

    When I read the book of "The Design of CMOS Radio-Frequency Integrated Circuits" of Thomas Lee, I want to get a model for hand calculate lna noise figure and linearity, I notice that there need some parameters, such θ and Esat.I use θ=2*10^(-9)/tox, but find it's accuracy is too poor. How can...
  6. R

    My adc chip has proper SNR, but SINAD is awfully low.

    maybe you can check your circuit to find harmonic distortion cause
  7. R

    ADC INL and DNL plots

    fdisplay real Matlab Code For Code Density Testing to Determine INL and DNL http://www.maxim-ic.com.cn/images/appnotes/2085/inldnl.m
  8. R

    Can we do offset cancelling like this?

    Comparing these two figures, I think you want to cancel the offset voltage of preamp and latch. but for conventional latch, when the latch works on 'nonlinear' . . when the switch is 'on' and the latch is in 'reset', the latch output is all vdd(or a common mode voltage), so the input voltage...
  9. R

    Anyone using symbolic simulator for circuit analysis?

    in matlab use 'pzmap' function to plot all zeros and poles in s plan
  10. R

    offset voltage about amplifier

    there is in your process match report
  11. R

    temperature impact on CMOS folded cascode op amp

    check your dc point, maybe some transistors have been in triode.
  12. R

    Anyone using symbolic simulator for circuit analysis?

    use matlab maybe the best here a matlab program to calcute the opamp transfer function.
  13. R

    a few questions about folded cascode design

    when you design a high BW opamp, the parasitic capacitor need be considered, such as cgs of M3. and the Cgs and gmbs of M9 when the compensation cap connected the source of M9 with the second stage output, because there is a zero at right plane, which affects your phase magin.

Part and Inventory Search

Back
Top