Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
about internal power
hi every one
I have a problem regarding internal power of Dflip flop. Actually i designed a FIFO, in
that i used registers. I extracted power (using PRIME POWER )of that FIFO by giving different switching activities of the input pins of the FIFO. Most...
help about primepower
(asic_designer): no i used switching activity 0.1 to 0.9 then also the percentage of switching power is less.
1)In my design 4000 registers are there and they are consuming most of the total dynamic power. Even if i gave 0 switching activity dynamic power shown by prime...
help about primepower
hi all,
iam calculating power using prime power. i found internal power is
80% of dynamic power where as switching power is only 20%.
iam using 90nm lib. iam manually giving the switching activities of
the pins (calculated from...
magma problem
hi all,
iam an mtech 2nd student from iitkgp. iam working on a project presently.
iam using magma for calculating power. Now iam facing problem in power
calculation, even though i gave different toggles it is giving same power.
when iam...
voltage variation
hi all ,
i have an architecture and verilog codes for all the blocks in that arch.
if i want to implement multiple voltage scaling techq to that which tool
will allow to vary VDD to find out delays at lower or higher VDD
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
