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Hi all,
I have implemented bidirectional IO in Max II as below:
//-----------------------
module bidir_io (
input wire in,
input wire oe,
output out,
inout wire io
);
assign io = oe ? in : 1'bz;
assign out = io;
endmodule
//--------------------------
I instantiate this module for bi-dir...
Hi guys,
I have an output port (reg) in a module. That module is instantiated in my top level module, with that output signal as wire to a pin on the CPLD.
I don't assign anything to this in my tb (since it would be an input into the tb).
But I still get the above error from Modelsim. The...
I have attached a portion of my code below; while running Modelsim Altera, I get the above error. Basically, based on the 4 bit dap_route code, I either loop-back some ports or route to outside CPLD (Max II).
module top_v (
//DAP1
inout wire dap1_fs,
inout wire dap1_sclk,
input dap1_dout...
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