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Recent content by ramagandhi

  1. R

    What are the issues faced when transition violation occurs?

    hi every one, can any one explain about transition violation issues? Thank you rama
  2. R

    How to calculate library setup time and Hold timel?

    hello every one, can any one explain about How to calculate library setup time and Hold time? Thanks in Advance RGR
  3. R

    If i get struck at 0 and struck at 1 faults after doing DFT what will i do?

    Thanks Maulin Sheth
  4. R

    If i get struck at 0 and struck at 1 faults after doing DFT what will i do?

    i am taking about SA-1/SA-0 for on tester..
  5. R

    If i get struck at 0 and struck at 1 faults after doing DFT what will i do?

    hi every one i would like to know If i get struck at 0 and struck at 1 faults after doing DFT what will i do? Thanks in Advance Ramagandhi
  6. R

    Synchronous & Asynchronous Sequential Circuits

    Thanqs Vimalraj205
  7. R

    Synchronous & Asynchronous Sequential Circuits

    What are the major differences between Synchronous & Asynchronous Sequential Circuits? Thanqs in advance.......
  8. R

    Difference Between VHDL and Verilog?

    Thanqs dava_59
  9. R

    How to fix DRC'S in physical design?

    Thanqs rca - - - Updated - - - Thanqs OhaAmo - - - Updated - - - Thanqs VijayR15
  10. R

    what do you mean by electro migration???

    Thanqs @rca - - - Updated - - - Thanqs @ohaamo
  11. R

    Difference Between VHDL and Verilog?

    Hi all, Please tell me difference between VHDL and VERILOG and using application area of both. Thanks.
  12. R

    What are decap,tap and endcap cells in physical design?

    hello every one can any body explian about dcap,tap and decap cells?
  13. R

    How to fix DRC'S in physical design?

    hello every one can anybody tell how to fix DRC's in Physical Design(PD)?
  14. R

    what do you mean by electro migration???

    hello everyone can u please explain about electro migration in physical design(PD)?
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