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I am designing a second order sigma delta modulator. I am using system vision tool from mentor graphics which uses VHDL-AMS for the analog circuits.
My fundamental frequency is 320kHz.
I am oversampling it by 64 times to get a 12 bit resolution at the 3stage CIC decimation filter output.
My...
problem with simulation
I am designing a second order modulator as shown in the figure. I am a newbie to analog and cant get a clue to find the resistor and capacitor values. Is there a logic to find the capacitor and resistor values. Even if I change the resistor value by 1 ohm i am getting...
that seems fine. but the quotient is always 0 or 1. what is important in my case is the digits to the right of decimal point.
for eg: it would be like 40/50=0.800
I can obtain the quotient i.e the left of the decimal just by subtracting the 2 numbers once, using the binary shift and subtract...
I am in need of a vhdl code which divides a 24 bit numerator by a 24 bit denominator.
The denominator is always greater than or equal to numerator.
So the value will always be between 0 and 1 and I require upto 3 decimal places
The numerator and denominator are both std_logic_vectors
Is is...
can anyone provide a VHDL code for square root for a 48 bit input std_logic_vector...
the link in csee.umbc.edu is for 8 and 32 bit... extending it seems complicated
how good is wipro vlsi?
i heard it does mainly validation/testing of circuits there...
i also heard that they have a reputation of changing the domain to a software job during the training phase even if one is selected through a vlsi panel during interview/selection procedures...
just wanted to...
ok i get that integration part... but will its ouptut be in signed magnitude or signed complement form
thanks for clearing the doubt over cic and sinc filters
i am designing a sigma delta ADC. I have completed a second order modulator. My frequency range is upto 40MHz oversampling. My required resolution is 12 bits and so i oversample by 64 times in a second order sigma delta modulator
My question is with the operation of filters... I heard that...
the frequency of my application is 50kHZ-sinusoidal waves.
i would require around 16 and at best 32 samples in a cycle so the sample rates should be around 1.6MHz at the output
we have not decided yet on the decimation factor required
what are the conventional types of filters used for this purpose?
i need to implement a sigma delta ADC with 12 bit resolution at the output.
The sigma delta design has the modulator part followed by the digital decimation filter.
i have constructed the modulator part in "system vision"
now i require the DIGITAL DECIMATION FILTER part in vhdl to complete the...
what is the difference between a serial and a parallel multiplier?
i need to build a VHDL code for 12 bit parallel multiplier in radix 4 booth algorithm
i want to build the digital system such that it uses a clk... can somebody help me?
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