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Recent content by rakesh02

  1. R

    pre cts in cadence pnr

    hi every one why we should add clock uncertainty in sdc after pre cts. how we should consider that skews
  2. R

    io buffers placments

    hi..., can any one explain why we need buffer at I/0 pins....what the importance of putting the buffers
  3. R

    wire load models worst slack

    hi., which wire load model (i.e,. zero or actual )..............which will have more slack........
  4. R

    logic synthesis performance in vlsi design flow

    how tool performs logic synthesis???????.....what is top down and bottom up synthesis?????
  5. R

    logic and physical synthesis

    zwlm-zero wire load model thanks rca.....please can you alobrate more in detail or do you know any sites.....???????
  6. R

    logic and physical synthesis

    in logic synthesis we use some models??? can any one explain why we should go for that?????? which model we should consider i.e., wlm or zwlm?????? how we should analysis the models???
  7. R

    logic and physical synthesis

    logic and physical synthesis in chip designing.......
  8. R

    logic and physical synthesis

    hiii can any one about logic and physical synthesis
  9. R

    static timing analaysis

    hi every one can any one explain about static timing analysis..... how we should solve the timing
  10. R

    internship in physical design

    Hi every one am going for a training in physical design for six months... after that what i should plan look for a job or a internship...am little confused please can any one help me.... and is there any openings for internship...
  11. R

    stick diagram using netlsit

    hi, can any one explain how to design a stick diagram using netlist . what are all the constraint we should see while designing a stickdiagram
  12. R

    Speed Checker for highways

    Can you provide data sheet...
  13. R

    Why phase locked loop(PLL) are asynchronous circuits?

    hi, can any one explain why phased lock loop (PLL) are asynchronous circuits.....can any one explain with example..
  14. R

    set up and hold violation

    hi every one, can any one explain about how to fix setup and hold violation.....and how to calculate the delay.......
  15. R

    What is the setup and hold time?

    hi guyz can any one share me the link where i can slove different problems based on setup and hold time and also on d flip flop......
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