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Recent content by rake

  1. R

    Do some one use Assertion Based Verification?

    I heared it many times,and it can improve productive,can some give me any suggestion? is it really action?and the learn curve is sharp?
  2. R

    Writing testbench in verilog or e language?

    If I can choose ,then Systemverilog,of course! It is the latest trendy,every vendor can support it and it is free.don't waste so many time in choose language.just throw your engery in finding your bug.
  3. R

    The Verification Language trend is Systemverilog

    systemverilog with vcs :arrow:we all know that,but where can i find the reference paper about it? BTW,which vendor support SV better?mentor or synopsys or cadence?
  4. R

    synopsys vcs question

    vcs mx Hi boy, Why you swith modelsim to vcs?I don't think it has any advantage,for me,all simulation tool are the same,but modelsim is cheaper than vcs. :?: rake
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