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Recent content by rajusripathi83

  1. R

    diffarence between fault coverage and test coverage?

    hi. please help me out..... please can any one explain whta is the diffarence between the fault coverage and test coverage....?
  2. R

    how a CAN controller works?

    please any one explain how a CAN controller works with block diagram?
  3. R

    Trimming of analog ic

    what are the units of area of chip ?
  4. R

    Trimming of analog ic

    in synopsys cell area is measured in micro meter square yes or no?
  5. R

    test point insertion technique

    please help me, iam getting c2,c24 s19, test-451 violations how do i rectify it.. in dft compiler
  6. R

    can controller synthesis problen

    hi ,,,, I have down can protocol synthesis using synopsys tool iam not getting the names in the synthesis . please help me..
  7. R

    rtl test bench error

    hi, plese help me repeat(100)@(posedge clk); for above statement iam getting following error Tasks cannot contain event control statements. *** Presto compilation terminated with 1 errors. *** please help me...
  8. R

    Controller area network (can)

    hi, help me with can protocol and controller..?
  9. R

    Controller area network (can)

    hi,, controler area network(CAN) controller ic has how many pins? what is the diffarence between can protocol and can controller are they same ? any boby can provide me the pin diagram of can controller? with i/o ports functionality? please...... thanking you
  10. R

    Controller area network (can)

    HI, In CAN rtl we have blocks like can_fifo.v can_bsp.v can_registers.v . . . what are they? can any body explain me the architecture of CAN. and block level diagram for CAN to write a verilog code? how to start a verilog code for CAN?
  11. R

    why do we rate transformers in KVA not in KW ?

    HI,, the reason is the Power of the load and its powerfactor.\\not all about the copper and core losses because we know that transformer is one of the most efficient electrical devices we have.
  12. R

    designfor testability test point insertion

    HIII...., what is the procedure for inserting test points in dft compiler?
  13. R

    designfor testability test point insertion

    hi... plzzzzzzzzzzzzzzzz..........any one can tell me theflow for inserting the user defined test points using the synopsys tools (dft and tetraMax). detailed flow... thank you
  14. R

    test point insertion

    a) sir iam not understanding the diffarence, first we will do simulation at begining stage using (vcs) ,why we again simulating in tetramax. coming to fault simulation we assume that the circuit is falty i,e by adding faults. b) sir for inserting test points we can use the folloing flow...
  15. R

    test point insertion

    thank you sir, 1) if we want to see the controllability and observability values what we need to do? there is any way? 2)what are the inputs for tetramax? ans :(stil protocol file, scan stitched routed netlist, simulatiom libraries) is correct or not? 3) in tetramax there is two options...
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