Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
dear gksivas,
We can have only Standard cell libraries. Analog libraries are not possible due to its changing specification.
Take correct file which will enable you to have all of metal layer required for respective technology.
diode protection vcc
Qus- when doing esd design for vdd/vss, we use the gate grounded NMOS. why is it so?
Ans- To protect the circuit from ESD event by using either up-and-down diode or GGNMOS.
Qus- i also came across design that have a R at its gate and tie to GND. what is the difference...
Re: Who got the answer for "The art of Analog Layout&am
hay......... so many question and answer (more than 100) are available in this forum. please search the keyword of your query, you will get it easily.
Re: question about the difference between the NMOS and PMOS
I do not think there is much differences. Diffremnce is that PMOS load use to load the current while NMOS use to supply the current. In the sense NMOS load work as a source and PMOS load use to get the output.
Re: Why Band gap reference is named so..... What is the reas
Hay, In my view energy gap between the valence and conduction band for silicon is 1.1V to 1.2V. If you design voltage reference circuit for this voltage range then you can say, it is bandgap refernce(BGR) circuit.
because digital is digital and it does not have high current in design.
Analog design has higher current so we need higher channel length to protect the transistor.
digital ckt is less prone about noise etc but analog ckt is very much prone to noise and other effect. That why we consider...
Hello,
Question on DRC and LVS is nothing but question about layout. This can be anythings like how to draw the layout for pmos, nmos, nand, nor, resistor, capacitor, gaurd ring. If you have better understanding of above then you will care how to avoid DRC and LVS problem while drawing layout...
Re: About electron migration
If the current flowing through a metal is greater than the current carrying capability of that metal,there happens a collision among the electrons which produces heat due to the collision which makes the metal gets melted causing a open circuit.
experience comes after bad judgement
and good judgement comes after long experience.
So, make mistake,
do it after failed again then you can be a perfect AMS IC Designer
Thanks!
Raj
Re: IR drop
Hi,
In my view, Voltage Drop V=IR
Here given that-
I= 100uA, So, we need to know the value of R. For that we check in design manual/foundary_provided_document that what is the value of metal resistance for unit area. Then we can use formula R_metal = metal length*metal width*metal...
Re: OTA design step by step
For proper understanding, you can use the Allen & Holberg book chapter 6 and 7. These chapter has spice code with model parameter also.
Example with solution, step-by-step is given.
You can copy and simulate the same code, which is given in chapter.
I hope........ in...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
