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Recent content by rajev_v

  1. R

    How do we define output of black box for clock domain crossing

    Hi Folk, How do we define output of black box for clock domain crossing in environment file? As input or output. and how it should be declared as asynchronous or related to any clock? Ex. In case of MAC rxd_i, collision, crs, rx_dv signals. Thanks
  2. R

    Blackbox output in cdc

    in env file, 1.output of black box should be declared as input? 2. this output should be declared as asynchronous or any particular domain?
  3. R

    reconvergence of clock domain signals

    A signal is crossing one clock domain and its feed to 2 other clock domains which are working on same clock.(fanout to 2 different domains) like: clk1 to clk2, clk1 to clk3. and clk2= clk3 following are some cases: please provide your views on those- 1: after synchronization in another...
  4. R

    reconvergence of clock domain signals

    a signal is crossing clock domain and its fanout to another2 domain that are working on same clock. and then after following are some cases: please provide your views 1: after synchronization in another domains signal is going to select line of mux, will it make any issue like reconvergence...
  5. R

    Clock domain crossing reconvergence

    What is solution for error in clock domain crossing, if re-convergence exist in design. are these waive-able or crucial?
  6. R

    Is this Latch or not?

    In the below image, the given circuit is considered as latch or not?
  7. R

    Difference between RAM & FIFO

    can any one please explain that what is difference between fifo and registers. except telling first in first out or pointer. any technical difference
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