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hi
in vhdl the for loop statement is used for itreation
but the if statement is used for conditional check
i think if statement is not replace by for loop satatement
Added after 3 minutes:
in if statement the specified condition is check but in the for loop statement the loop is start...
In this program if 'run' mode is out(output port)
then u not put into the process() sensitivity list
or if run is variable then you use variable assignment statement for assiging the value.
like
run := en_aq;
it is depend upon the what is the data type of the din
if din is bit type then
if (Clk1'event and Clk1 = '1' )then
dout <= din and clk2
its working
and if the din is integer type or any other data type then u can use one clk as clk signal and other one is used as a enable...
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