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verification is convergence of intention, specification and implementation. This means verification is task of verifying whether the intended behaviour is captured in specification and the features captured in the specification are implemented in RTL or not.the intended behaviour...
if i have so many signals with different delays then there will be so many counters. If i synthesize the code there will be so many counters created. what about the performance of the module?
Thanks.
Hi,
I am new to this group. I am new to design.
How can i design a module that consists of synthesizable delays. For example after assertion of "en" signals wait 2,3 or 4 clock cycles and then assert "strobe" signal. The delays are programmable. How can introduce the synthesizable...
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