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Hi everyone,
After running Spyglass, I'm seeing a couple of errors being reported on logical OR operation.
Posting an example here:
wire [5:0] a;
wire b, c, d;
assign d = c & (a || b);
I had this code initially, so the initial error was that the operator || has a width mismatch on...
Yes, the plan for the current design is to have the writes from both the input streams at the same time. If not, then it would be difficult to maintain the ordering of the inputs at the output stream when both the input streams have different write timings.
--- Edited to answer the part about...
I am currently working on a design which requires me to design a module that combines 2 input streams of data & output it into a single output stream. To elaborate more, i can describe it with an example :
CLK
Input Data Word 0
Input Data Word 1
Output
0
a
b
-
1
c
d
a
2
e
f
b...
Sorry about this one, I posted this question in a hurry without checking the width of a & b in code. As it's a phone interview, the question was just multiply a 9 bit register & a 8 bit register - what's the outcome. So i just remembered my answer of 17. My apologies for writing a 9 bit reg as...
Hi,
I was recently asked this question in a Logic Design/DV interview,
Suppose you have the following, what should be the bit width of c,d,e ? The interviewer said that the answers of my d & e were wrong. For e my answer was based on 3 as 2'b11 which would give a width of 18. What do you guys...
Hi all,
I'm trying to clk gate a few registers for saving power & couldn't understand the following. Below is a snippet of what I've tried
Method 1 : where i explicitly coarse & fine gater
always @(posedge clk) begin
for (i =0; i < 255; i = i+1) begin
if (we[i >> 5] & coarse_en)...
I was reading a paper from MICRO which says the following :
I understand the part where he says that TOMASULO is inefficient as it uses reservation station's ID till the instruction commits. But, i don't understand the statement
After years of reading about CPU uArch, I want to start learning about GPU pipelines & unfortunately ARM infocenter isn't helpful in this case. So, any good recommendations as to where I can start to learn about GPU pipelines ? Not trying to learn deeply about Shader Core, but in general GPU...
Suppose, I have a vector:
logic [127:0] x; // one hot
I want to OR the even bits & odd bits seperately, as in x_even = x[0] | x[2] | x[4] | ...... x[126] & similarly for the odd bits. I tried the following but it's pointing a syntax error at |=
generate
for (i=0;i<64;i++) begin
x_even...
Hi,
I had a basic question, as in what would be the dimension of the o/p after performing a reduction operator on a multidimension vector ?
Sippose I have a vector,
logic [1:0] test [5:0];
Would |test give a 2 bit o/p ? or would it also do a bit wise OR of all bits to give a single bit ?
I understood the error, there was a missing end .. statement. Not sure why it didn't raise an error
always @(count,out2_complex_bf1,out2_real_bf1) begin
if (count >= 4'b1000) begin
out2_real_bf1_t <= out2_complex_bf1;
out2_complex_bf1_t <= (~(out2_real_bf1)) + 1;
end else begin...
Hi,
I am multiplying two variables (16 bit) in verilog, so the maximum number of bits of the product is 32 bits. Is there any shortcut to assign the msb 16 bits to a variable ?
parameter a = 16'hABCD;
parameter b = 16'hFFFF;
wire [15:0] c;
assign c = a*b;
c will be assigned the 16 lsb...
Hi,
I am trying to do the following in Verilog: if count < 8, pass the i/p to o/p, else multiply the i/p by -j. Note: i/p is a complex number.
My code:
always @(count,out2_complex_bf1,out2_real_bf1) begin
if (count >= 4'b1000) begin
out2_real_bf1_t <= out2_complex_bf1;
out2_complex_bf1_t...
Hi,
I have a spice file like this:
**Test inverter
.TEMP 110
**Use high temperature to simulate worst case delay and leakage power
.OPTION
+ ARTIST=2
+ INGOLD=2
+ MEASOUT=1
+ PARHIER=LOCAL
+ PSF=2
+ POST
.inc...
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