Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by Raagasudha

  1. R

    Verilog beginner doubts

    Also, while forcibly breaking the simulation, the execution is at the clock inversion line (clk = ~clk). There are no warnings or errors in compilation
  2. R

    Verilog beginner doubts

    ok, here is the code that is hanging: ----------------------------------------------------------------------------------------------- module sipo_tb; reg d,clk,clr,reset,check; wire q1,q2,q3,q4; reg [3:0]t; integer i; sipo dut1(.d(d), .q1(q1),.q2(q2), .q3(q3), .q4(q4), .clk(clk), .clr(clr)...
  3. R

    Verilog beginner doubts

    Hi, I wrote a design and testbench code for PIPO shift register. I have instantiated four dflops in the design. I noticed something strange.. If I use this construct in the testbench: always ---- ---- I=I+1; if(I==20) $finish; end the compilation is fyn but the execution sends it to infinite...
See more

Part and Inventory Search

Back
Top