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Recent content by r_p_sanna

  1. R

    Interfacing Matlab model with Verilog

    Any body help me out how to interface matlab model in Verilog. The objective is like I have a matlab model which gets the input from the verilog and generates output. Verilog needs to use the Matlab output for further processing.
  2. R

    Aurora bus specification and protocol

    Aurora bus specification Hi, this spec. is an open standard. are there any companies which provide this IP ?
  3. R

    How to start learning SystemVerilog

    systemverilog learning i think it ll be possible to download the systemverilog LRM from this link http://www.eda.org/sv/SystemVerilog_3.1_final.pdf
  4. R

    Can someone provide an workshop of JupiterXT

    when i wanted to try out primetime, the solvnet had a hands-on tutorial on that. it was downloadable from solvnet and the constraint files and the netlists could be obtained from the PT installation directory. is this possible with jupiter?
  5. R

    Can someone provide an workshop of JupiterXT

    yes, you are right. I'm providing the link where it can be downloaded. Sorry for the wrong link. http://www.snug-universal.org/cgi-bin/search/search.cgi in this, search for jupiter and download the presentations. should be sufficient i guess
  6. R

    How to transfer the data from PC to FPGA Board thru RS-232?

    UART hi, if i'm not mistaken, if your development board has a UART, then find the pinouts of that, and instantiate it in your vhdl design. i believe this must be the procedure. also, is it a custom board which hosts the fpga or is it a development board offered by some company ? coz, if its...
  7. R

    implementation of software in FPGA, Xilinx

    hi, you will need to compile the software in a fpga which supports processors, i think spartan supports soft processor called microblaze(not sure of it though). couple of other fpgas such as virtex-II, virtex-II pro and virtex-4 families support powerpc(hard IP) and microblaze(soft IP). if you...
  8. R

    Creating LEF to pass on to the backend tools

    Regd: Creating lef hi linuxluo, yes, i agree with you about creating lef. this is almost like backtracking. What i was thinking was, along with the netlist, if it has memories, then, a lef will be given so that the memory can be made into a blackbox in the netlist during the semi-custom flow...
  9. R

    What are the differences between OASIS and GDS ?

    Re: OASIS hi, as far as i know, its a format just like GDSII, only a lot better. I've added a document along with this mail. Hope it clarifies
  10. R

    Tips for test benches????

    this is the link for a book called "verification methodology manual" by david dempster and micheal stuart **broken link removed** let me know if this is helpful
  11. R

    Getting started w/ ASICs - request for resources

    Getting started w/ ASICs ASIC book can be read online. here is the link **broken link removed**
  12. R

    Getting layout of a circuit from schematics

    help on layout design as far as i know, even to get the layout in digital schematic, we feed the netlist and not the schematic.
  13. R

    Error when trying to do sroute

    sroute gets error Sroute command might not be correct.During Sroute we have to give net name and option. Added after 2 minutes: an example : sroute -BlockPins -PadRings -CorePins -noStripes -jogControl { preferWithChanges differentLayer } -nets { VSS VDD }
  14. R

    How to write a logic in Verilog for creating a latch?

    latch in verilog thanks. i was thinking in lines of, if i don't create the default in case statement, latch is inferred. is there any other way that a latch can be inferred ?
  15. R

    Can Verilog produce data other than net and wire ?

    verilog integers, real, time units, parameters and arrays too i guess

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