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FvM, thank you again for your very helpful and instructive reply.
Ah, totally fascinating; I get it. The drill strikes a void in the FR-4, thereby exposing it to the outside air; once exposed it gets electroplated, creating a short if the drill was too close to any copper.
Yes, I can see why...
Yes, I know what you're talking about. And it's stupid.
If the PCB house is paying some highly-trained human to manually look at my boards, they're Doing It Wrong. There is no way they will be cost-competitive for my weekly 10-board prototype runs (which I do MONTHS of before placing the big...
Evidently not because you have only just now figured out what I was asking.
This is exactly what I have been doing.
This thread asks the question: does the worst-case allow to omit annular rings from inner layers? And if it does not, what failure (specifically) could result from omitting...
Uh, yes... that was exactly my plan. You know, experimentation.
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Barry, please re-read the thread. I can't afford to be locked in to a specific board manufacturer, so asking any specific board manufacturer -- no matter how "reputable" -- if their specific fab can do this...
Well, I don't want to be tied to a single PCB manufacturer, so I'm looking for a general manufacturer-agnostic answer.
Sort of like how if you stick to 0.15mm trace/space and 0.3mm drills you can get your board made cheaply just about anywhere. There's a certain baseline spec that works...
Does anybody know where to get simulation models for GDDR5 components?
Most of the memory foundries post (encrypted) HSPICE+verilog models of their DDR, DDR2, DDR3, and DDR4 parts for public download without so much as a login. But I've been totally unable to find any GDDR5 models!
For...
Suppose I have a via in a four-layer board, and the via connects to traces only on the outer two layers. Is it okay to omit the annular ring from the inner two layers? Will this cause problems when plating the through-hole, or is the annular ring part of the plating process only on the outer...
Hi, can anybody recommend a good RC extraction tool that comes from somewhere other than Cadence/Mentor/Synopsys? Their licensing terms are outrageous and conflict with our network security policies.
Doesn't have to be freeware, and probably shouldn't -- I'm happy to pay for it.
Just needs to...
Re: hsim multithread
Yes, since around 2009ish. Pass the flag "-mt" on the command line. You'll see a line in the log like this:
MT: evaluation of 385/3124 sub-devices will be parallelized
When it works, it's great. Unfortunately how it decides which sub-devices are eligible is extremely...
Hi, does anybody know how to go about setting up an account with UMC?
We tried the obvious, emailing sales@umc.com as shown on their website; no response.
We need a spot on the next 55nm shuttle run and, if successful, an MLM maskset for production in the 50-100 wafer range.
It's a very straightforward "all polygons on layer X must have area greater than or equal to Y" rule.
RULE {
detect = METAL1 AREA < Y
}
Unfortunately looking on that layer isn't enough. Nets cross layers. For example, if you have a VIA polygon then the polygons on the metal layer above...
When they FIB through the back of the chip, they're basically blasting a 5um wide hole in the silicon. So any transistors in that area are destroyed.
Yes, that's the idea.
Hi,
I've been reading about and SPICEing a lot of current mode logic (MCML) lately, and I find it really fascinating.
However, all the papers I've come across use a DC tail current.
Is there any work on current mode logic (preferably MOSFET but not necessarily) using an AC tail current? The...
Ask around for "flip chip FIB". There are companies that can FIB in from the back (substrate) side which would get you to metal-1 without disturbing the metal above it (which probably carry power, clock, etc).
Of course this will utterly destroy any transistors underneath the metal-1 you're...
I'm posting this here so Google (and other designers) can find it. This burned up at least a week of my time and I couldn't find *anything* about it anywhere on the web.
I have a design that is LVS-clean (using Calibre) and extracts correctly via Star-RCXT as long as calibre was NOT run with...
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