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Hi,
regarding 1.)
2FF synchronizer are ok.
Because, if you go from fast to slow clock. You will not get every pointer value on the slow side. But due to the gray coding you will always have a stable value. With this the remaining logic is ok and stable.
Regarding 2.) You are right. The full...
Hi,
you will need a library which is characterized for 1.0V
with this library you can do your synthesis and your sdf simulations.
Depending on your position regarding the foudary you may get this library or not.
Or maybe your foundary does have a tool for derating an existing library.
Maybe...
If you look at the first picture of the link
https://asic-soc.blogspot.de/2007/12/new-asynchronous-fifo-design.html
you can see that you have the wq2_rptr which is in the same clock domain as the wptr and you have the rq2_wptr which is in the same domain as the rptr
regards
Hi,
yes you are right, the path with the mux will be a false path. So in theory it could be long. I think to be on the save side you need to make a constraint, which makes sure that the delays trough the mux is not longer than ~ 1clock cycle.
regards
The flop on the read side will only be metastable if the D input of the flop changes during the clock rise time (in the setup/hold window).
But in the design the multiplexer always selects a write flop which has a stable output when the read flop latches the data.
The written data on the write...
Hi coolasic,
I think we have a different understanding of the structure of the fifo. I attached a picture.
The write side writes into entry 0,1,2,3,4,0,1,2,3,4,...
The read side reads at the same time from 3,4,0,1,2,3,4,0,1,....
If the clock phase is shifted the readout may be one entry earlier...
Hi coolasic,
you are right, you will need a simple asynchrnous fifo.
You have continous write and read data.
So your write and read pointer increases with every clock cycle. So you "just" have to make sure that the two pointers start after reset with the correct offset.
You can do like this...
Hi,
for question 1.
the output of one FF is constant high, the other FF is toggling with clk/2 frequency.
for question 4.
assuming the inverter gives you an delay
F1 is AND or OR
F2 is XOR
regards
Hi
critical for latches are combinatorical blocks.
when I look into your always @(*) block with the big case the states
grantX will generate latches.
e.g look into grant4
grant4: begin
stat=4'b1000;
if(req4==1'd0||pri_change)
begin
next_state=idle;
end...
Hi,
I think in addition you can not use the if
you have to write
assign out = (c==1'b0) ? x1[7:0] : x2[7:0;
or you do it in an always block
e.g.
always@( * ) begin
if (c==1'b0)
out= x2[7:0];
else
out = x1[7:0];
end
regards
It is not clear what you mean with BT 656 decoder
you can download the ITU 656 recommendation from the ITU internet site
https://www.itu.int/dms_pubrec/itu-r/rec/bt/R-REC-BT.656-5-200712-I!!PDF-E.pdf
regards
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