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Hello Here are my specs
I have been asked to design a LDO. Vin range : 1.62-1.92V, VOUT: 1.4V (3 sigma), Current range: 100u-100mA in 100nsec, Vref: 0.8V( 3 percent +/_), CL=1uF, BW of the Amplifier=5Mhz, gain=6000v/v . I took all these specs and simulated in cadence in all the possible corner...
Hello, I am designing an LDO. I am using two stage opam as error amplifier. I am connecting the output of opam to the gate of pass transistor. How to calculate load cap and Slew rate for opam calculation,l
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