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following branches form a loop of rigid branches
hi friends,
i got this ,whenever we choosing vdc source we define value of it too ,so in the global source option we should not give the value of dc source . if we giving the value here too then this shows fatal .error
cdscd negative
hi ,
i m making a asynchronous fifo in cadence .at the time of simulation this is giving the same error. if it is not according to the particular process technology parameter then what should i do for this .
plz reply as soon as possible .i will be remain very thankful to u.
rigid branches (shorts)
hi macg84,
how u resolved this problem ?bcz i also phasing this problem . in hierarchy to give the globle sources input i m using vdc in between vdd and ground . and gave the value to vdc to =5 volt . and the stimulus window i again givine the value to voltage source 5...
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