Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hello all
I wander if it is possible to use Verilog/VHDL testbench in Tetramax.
Or is there any way to convert Verilog testbench to a format like STIL, readable to Tetramax?
I need to do this to run fault simulation on a sequential circuit w/o scan chains.
Any help is appreciated. Thank you
You can use
set_patterns -external test_pattern_file
After that, I would use run_simulation to simulate these patterns.
Then use run_fault_sim to get fault coverage.
Hello
I would like to ask if synthesis tools like Design Compiler or any other tool can separate the desciption of controller and datapath in RTL designs.
What I mean is the tool can read RTL design file (VHDL/Verilog) and visualize/output description files for the controller and the datapath...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
