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Recent content by prassingh

  1. P

    Runt clock pulse on a flop with static input

    Yes that's what I wanted to confirm . Thanks
  2. P

    Runt clock pulse on a flop with static input

    I'm working on some scan-debug flops where I need to switch between test clock and functional clocks. Input of such flops will be constant at time of switching . So if there will be a glitch even though data is constant there will be corruption of data in the chain. So that's why I wanted to...
  3. P

    Runt clock pulse on a flop with static input

    I'm not designing any schematic. I wanted to know this because I wanted to switch between asynchronous clocks to the flops . It is guaranteed that input will be stable at time of switching. So if there will be glitch then certainly I need to gate clocks before switching and if not then there is...
  4. P

    Clock tree dynamic power

    Generally the leakage power goes high when you reduce Vt of a CMOS transistor . So if you are using low Vt cells on clock paths then your power will go up. But the advantage is low vt cells are faster . You would see good transitions on clock path with low vt cells . So you need to make a...
  5. P

    determining latency in clocks

    I'm not sure what actually you want to find out. But latency is generally seen on full clock path (from source of clock {generally pll or pads} to clock end-point {flops or pads}) . So once you have full path you can just use up delays specified in libs and compute latency {should use PT for it}
  6. P

    clock and reset design structure for SOC or Lower Power SOC

    I don't think using up of PLL stable signal as a reset is good design methodology. When you would be doing dynamic frequency change in a PLL the stable signal would be toggling and this would lead to reset assertion/deassertion, which you don't want. So better way would be to create a reset...
  7. P

    Runt clock pulse on a flop with static input

    Hi, Will there be a glitch on output of a D flipflop when a runt pulse is applied to clk pin. The input data is assumed to be static.
  8. P

    Clock tree dynamic power

    Hi I needed to know how much does clock physical distribution affect the clock tree power . Is it too much dependent on number of distribution stages of clock or just the loading on final distribution stage How can I optimize the clock tree dynamic power just by changing physical distribution ?
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