Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi All,
On what parameters Wirebond and Flipchip Die bump pitch are decided?
I have seen most of the WB die pitch has min of 50um and FC Die has 180um .
Would like to know on what standard it has been placed? Whether PD engineers aware of Packaging layout?
Thanks for the time.
Hi All,
Pls tell me , how much spacing shd i provide b/w high voltage traces? for ex: if trace is carrying 100v.
We know that trace width is depend on current carrying, how abt trace spacing for high voltages?
Also, what shd be trace spacing between high voltage trace and signal trace, also...
Hi All,
Am fresher. I would like to learn Physical layout design by own. So kindly fwd me some nice presentations to begin and work with.
Also let me know , what are all tools used for it ? For schematic and layout, Cadence virtuoso is widely used?
- Thanks
Hi RfP,
Thanks for your reply. After providing that RLC of package, will you carry out any test/simulation? Can you name those test methods if you have any idea.
Hi All,
I work in ic packaging layout. Recently, my client came out requesting for generating Parasitic(RLC Parameters) of Package pins i.e for solder balls. The package is wirebond package.
Now, my doubt is what they do with RLC value of package pins? Just to create IBIS model for the...
Hi All.
I have some experience in Signal integrity at pcb level and IC package level and would like to broader my career . So , am thinking of learning Static Timing Analysis.
So guys, pls help me out with any tutorials . I know Primetime tool has been widely used, apart from that...
Hi All,
There is any guidelines available for component placement in pcb with respect to Design for Manufacturing(DFM)?
what and all precautions need to be taken care during component placement w.r.t DFM and if there any materials available. Kindly pass it on.
Regards
Pr
2. Logic - Assign net, click on Die-pin that which net u need to assign to ball pin,,, then again click on the bga ball, so the particular net what u want can be assigned.
1. Make sure the padstack you defined for VIA is correctly linked and available, also vary the parameters , so you can do...
No idea George. But, Why dont you use Waive DRC? its simple to use. It wont display any drc's physically even though it say's there are some drc's which have been waived when you generate reports... Goto Display-->Waive Drc ---> waive.. Hope you will be knowing this.
Yes, George. You are right, drc can't be removed. I use Route Keepout instead of route-keepin for all my design. Hope, you will be knowing, anyway i attach the file for ref .
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
