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Recent content by Pramod

  1. P

    how to convert a spice netlist to a schematic?

    it is possible you can import netlist using FILE->import in Cadence CIW
  2. P

    understanding meaning of DRC errors

    Hi, If u r using hercules they provide some pdf files about these drc error explaination.Go through these pdf files. Regards, Pramod
  3. P

    What is the main application of Perl language?

    Re: perl usage... Hi, we can use perl to do some file processing.But with this we cant generate blocks in layout editor.If u r using cadence try skill language.It helps to automate the layout. Regards, Pramod
  4. P

    What is CMOS Latch up and how to prevent it?

    Re: CMOS Latch up Low resistence between power signals is called latchup
  5. P

    How to verify the DRC of different power supply transistor

    Re: How to verify the DRC of different power supply transist Hi Hughes, What is this ID layer?
  6. P

    layout designer responsibilities

    hi wdd, what is LPE
  7. P

    layout designer responsibilities

    hi, Other than the layout design, what are the other layout designer responsibilities.Which are the other tools he should know including layout editor. Thanks in Advance Pramod
  8. P

    What does Mult. means in a schematic?

    what is the meaning of matching?
  9. P

    Technology files of the 0.35u, 0.18u or other technology

    Re: technology files Hi, Try it in TSMC website in tsmconline.I think you need to register for that.Try it once. regards, Pramod
  10. P

    differnce b/w bumps,pads,and IOCELLS

    hi, What are the exact meaning difference b/w bumps,pads,and IOCELLS. Do we need bump cells in PBGA package.? And what are the uses of bump cells? Thanks in advance Pramod
  11. P

    about probe pad or probe window?

    Hi what are these probe pad and probe window can any one help me to understand
  12. P

    Differences between C4 pad and BGA pad

    c4, bga Pad structure contains all metals ie from bottom to top metals.Bumps are designed using top metal. Genarally pad structures are used for PBGA type packages bump s are used for FCBGA packages
  13. P

    viewdraw to cadence conversion

    viewdraw Hi, I have a schematic in viewdraw.Is there any way to convert viewdraw schematic to cadence composer schematic.If so inform me please. Thanks, Regards Pramod
  14. P

    Round-robin and priority arbiter, which is better?

    arbiter round robin priority arbitor
  15. P

    How to convert from RTL to gdsII to vhdl code?

    Re: what is GDS-II? its a binary fole format for layouts
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