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Re: ic fabrication
After a layout is complete, a check for design rule violations should be made before the layout is sent to the chip foundry for fabrication. If a chip is fabricated with design rule violations, it may fail to function as designed.
Circuits must be free of DRC errors for...
why pmos is used as pull up
A pull-up device when energized will pull the ouput to supply(i.e "1") and a pull-down will pull the output to ground (i.e. "0").
Usually PMOS is used for pull-up since it can provide GOOD "1" (HIGH) i.e VDD and
NMOS is pull-down since it can provide a GOOD "0" i.e...
cds.lib
Hi
We use the cds.lib file to point to the reference and design
libraries we want to use in our design.
The information in the cds.lib file can be seen & modified through Library path editor (cdsLibEditor).
For more information on the cds.lib file, refer Cadence Application...
Hi,
I have worked on Microwind, L-Edit for layout design. Currently, am using Cadence Virtuoso Layout Editor. Comparatively, Virtuoso is the best and user's friendly.
Re: Is layout job boring?
Hi
I am working as analog layout engineer from past one and a half year. With ref. to my experience, really it's a creative art. Am sure, you will enjoy the work.
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