Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Dear All,
I am quite new to HFSS and Antenna world, and just done some simulations with Antenna following some tutorials. I have some questions here, thanks for your helps:
1. When the radiation pattern is generated, which frequency does it work?
I suppose radiation pattern varies as changing...
Dear Friends,
As you may know that, the chip edge has to connect to some voltage level or the DRC will report the error, so I have done my Chip edge as below:
as illustrated, the chip edge has been connected to the LNA_GND, I hope this should be all right.
And furthermore, I have simply...
Usage of the Inductor From the Standard Library In CMOS Technology
Dear my fellow designers,
I have been curious about the Inductor in CMOS Lib for quite a while. As you know, the inductor's ground plane should be contacted to some voltage level, and in my case, it should be the voltage level...
Hi dick and all,
Thanks for your great helps. Just some follow-up question,
In the library, I have seen the ESD_DIODE_STRING which simply series more than one diode, can NOT figure out the meanings of it. On one side, it seems to have doubled the avalanche threshold voltage, right? Say...
Dank WimRFP,
Actually this is for the research oriented prototyping fabrication. I dont wanna take the risk either, but the clock it ticking, very close to the tapeout's last minute, not really enough time to figure out a really robust ESD which suits my circuit. So I have to put some ESD...
Dear Friends,
Just recently found out an issue about the ESD protection when designing a transmitter with about 20 pins, the 8GHz centre frequency RF signal's output waveform has been really twisted after adding the ESD protection circuitry, I suppose this is due to the parasitic or something...
Dear Friends,
I have been tricked by a LVS error for such a long time now, and really expect some helps from you guys.
In the circuit where a large value poly resistor is employed, instead of setting a single bar, I have made multiple bars for it so that the resistor looks closer to a square...
Virtuoso Layout Off-Grid-Shape Error, After Drawing The Metal Path in Diagonal Snap
Hey friends,
No 45 degree shape is allowed in some process, but my question is, why the inductor from the standard library has the 45-degree angles? How could the foundry manage that if it can NOT allow the...
Hi Erik,
Dank, dank. Really helpful advice I have been appreciating.
I have checked the directory of /tools/cadence/ASSURA04.12.001-5141_lnx86/tools/assura/bin/assura,
Actually assura is a file, after opening it up, the first row is #!/bin/ksh
What does it mean? I am so confused here now...
Hey Friends,
I am currently using 0.13um CMOS process, and the Assura tool for DRC/ERC/LVS, under the Cadence icfb5141.
All the set-ups for 'Run Assura DRC' are exactly as what has been described in the foundry's training tutorials, fishy stuff happens when pressing the button. The error...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
