Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
site:edaboard.com encrypt verilog -search results
It is possible to encrypt HDL design files for functional simulation. How I can protrct my design during synthesis? I want to give the customer a file, which is synthesizable but its content is not viewable! How I can do it?
Any help?
Also I want to know the compelete flow for ordinary designs and tools?
What is the start point and end point? Is the ouput of tools GDSII or more post processing is needed?
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
