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Neither bit rate nor length can be reduced. I need 10Mbps at 1500 meters.
I realized that VDSL is a good solution for my needs, Manufacturers like "Metanoia" have products in the field, but I haven't been able to find parts with complete datasheet from that company.
Can anyone please...
I'm going to use FPGA or eventually ARM to control the chip.
Has anyone had the experience of running ADSL / VDSL chips with FPGA or ARMs? And can anybody introduce a chip that doesn't have the complexity of a startup?
Data Transfer over long twisted pair cable
Hi Guys,
I need to have a high rate data transfer of about 10Mbps on a twisted-pair wired line over a long distance of about 1500 meters.
From my searches, I came to the conclusion that over the long haul, protocols like the RS485 did not meet my...
Hi,
I have a kintex7 custom Board with xc7k410tffg676-2 device.
it has a connection to sata port.
MGTREFCLK0P_116/MGTREFCLK0N_116 is connected to a 200MHz ref clk(pin D6 and D5)
SATA data ports are connected to MGTXTXP0_116,MGTXTXN0_116, MG4 MGTXRXP0_116 and MGTXRXN0_116. (Pins F1,F2 , G3...
Vivado debuging and keep attribute!
Hi,
It was so easy for me to use ChipScope for debugging, but in vivado I've problems?
naming signals in code and finding them on vivado debugger is not easy.
in debugging by vivado, names of signals changes and it is not easy to clarify the signals I...
this is not true, because I "set as top" in both(ISE / vivado), then there is no need to connect iAddr or iClk to anything!
I'v attached the projects of Vivado and ISE for who is interested in testing the design.
Not any ROM extracted. in vivado synthesize finishes with NO Error but not any ROM is extracted as report.
By opening synthesize result netlist and viewing schematic I see no ROM extracted and all output port is connected to gnd.
I've attached ISE and vivado synthesize report.
Hi,
I have a code for extracting a ROM from a text file. I'v used it successfully in ISE 14.7 on a spartan6. synthesize and implementation was OK.
but now I want to use it on an artix project by vivado. unfortunately vivado can not synthesize the code currently .
the code is as below...
Re: help in encrypting or obfuscation of a design!
Isnt it possible to modify a NGC file? perhaps in vivado by commands like write_vhdl!
I think if one can modify a NGC file, it will not be so difficult to assign a '1' to my OK signal.
Re: help in encrypting or obfuscation of a design!
I'm tying to block unauthorized access to my design. I have add a design that checks some conditions and if met, an OK signal is made.
I think that if any one can read netlist, so he can find this OK signal and change it value!
Hi,
I have a design in mixed language (VHDL,Verilog)!
I want to deliver it to my customer to be used in Vivado.
1) How can I encrypt or obfuscate it to be used as a black box in vivado?
I made .dcp or .edf files that can be added to vivado, but these are netlists and can be read by anyone! by...
thanks for all replies.
Storing information in FPGA by myself(like registers or ROMs) is not the case I'm looking for. I want an automatic method.
I thing ICAP could be a solution.
Hi,
I want to know is it possible to find current FPGA family with a logic inside FPGA?
I know some about ID CODE in Xilinx FPGAs, is it possible to read it inside FPGA for this purpose?
My question is about both Altera and Xilinx FPGAs!
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