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Recent content by pooja_khubbar

  1. P

    can admiitance be negative

    thanks WimRFP & zorro "even a serier resistor has negative Y12 and Y21 parameters".. it means resistance is negative and hence admittance... i understand the explanation given for 2 terminal devices but not for two port nwk.. what is the meaning of negative resistance here and why it came and...
  2. P

    can admiitance be negative

    i want to knw that for a simple dc ckt , can value of admittance be negative. if so how.. i solved a numerical and found its y parameters for a two port nwk and value comes out to be negative which is same as in book...
  3. P

    how to choose device properties in ise8.2i

    Dear all.. am using ise 8.2i and the device properties i choose are • Device Family: Spartan3 • Device: xc3s200E • Package: FG320 • Speed Grade: -5 • Synthesis Tool: XST (VHDL/Verilog) • Simulator: ISE Simulator (VHDL/Verilog) • Preferred Language: verilog because these properties are...
  4. P

    two 4bit no. when multiplied results in max no. of 1s

    thanks all..for the reply..in my case am taking unsigned no.... and its not a homework or assignment..am trying to design some multipliers and then i ve to evaluate the performance of dyanmic ckt..and am using simple binary no.s
  5. P

    two 4bit no. when multiplied results in max no. of 1s

    hello friends can anyone tell me two 4bit numbers....whose multiplication leads to maximum no of 1s in output.
  6. P

    why we need test benches in verilog

    hello friends i want to know why we need test benches in verilog..as we can easily check the outputs by forcing values through modelsim..plz explain me the reason...
  7. P

    [SOLVED] problem with code of hamming encoder and decoder

    --encoder parameter n=11,k=7; output [n-1:0] out; input [k-1:0] in; input reset; reg [n-1:0] out; integer i,j; always @(in or reset) begin if(reset) out = 0; else begin i=0; j=0; while((i<n) || (j<k)) begin while(i==0 || i==1 || i==3 || i==7) begin out[i] = 0; i=i+1; end out[i] = in[j]; i=i+1...
  8. P

    [SOLVED] what is the need of fpga imlementation

    am doing a project in which k bit data is encoded into 2exp(k-1) bits of orthogonal code..and then decoding it...i have simulated the design using verilog..my results are found to be correct and now i hv to implement it in fpga..it means some errors can affect its working while implementing it...
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    [SOLVED] what is the need of fpga imlementation

    hello friends i want to know after code testing and simulating it in hdl language..whats the use of fpga implementation.. mean what additional information we can get by implementing in fpga..
  10. P

    how to create look up table of orthogonal codes

    hi all am doing a project in which in transmitter i ve to use an encoder...for this a 4bit code is converted into 8 bit orthogonal code through look up table...can anyone tell how to convert it i.e how should i create a look up table... and please specify for higher bits also the picture...
  11. P

    verilog project needed

    please can anyone can send a project on verilog which cud be submitted as dissertation....its quite urgent..it can b on communication, power saving methods or anything dat comes under sensor networks
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