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Recent content by Ponmalar21

  1. P

    design layout in TANNER

    Can anyone help me to design the layout in TANNER EDA tool L-edit..If there is any link for this procedure??
  2. P

    [moved] Error debugging in vhdl

    Debug the error in the following verilog code: module ring_count(q,clk,clr); input clk,clr; output [3:0]q; reg [3:0]q; always @(posedge clk) if(clr==1) q<=4′b1000; else begin q[3]<=q[0]; q[2]<=q[3]...
  3. P

    delay calculation in vhdl

    How to generate random delay in the VHDL code??
  4. P

    Interfacing FPGA with SPARTAN 6

    Hi sir, Can you help me. Iam using SPARTAN 6 EDK hardware for implementing noise algorithm for images. Can you tell me how will i connect the hardware to PC to see the image output.What software we have to use to show the output image??
  5. P

    CMOS Power dissipation

    What is the main reason for CMOS having low power consumption compare to P-MOS and N-MOS?? Is there any fabrication difficulty in that??
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