Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I want to update the value of a signal which is struct. I create a struct variable v2
and i update its fields. Afterwards i call the write() function on the v1_sig with v2 as an
argument. Then i call wait() (the code is in a SC_THREAD being sensitive to a clock)
to let the signal being updated...
Hi,
i have none background w.r.t. antennas. I have a very simple question.
I have an antenna which is supposed to work at frequencies 5.4-5.85Ghz. I also have equipment
for communication between cars which ends at an SMA connector and i am
supposed to connect an antenna operating at frequencies...
Hi,
i have a module and i want it to be tech mapped to a specific standard cell
each time it is instantiated. Is there a corresponding directive in DC?
Thnx
pmat
Thnx for the response,
I went through some sites and i saw that GPS modules targetting relatively slow moving objects like pedestrians or whatever go with a 1-2Hz update
devices. Now, GPS devices which are more suitable for high speed environment like racing etc. usually go with 10Hs update...
Hi,
we are building an automotive project and i want your opinion in some issues:
1. GPS Module: We are interested in a module capable of generating output
not only for low speed environments (city traffic) but also for highway velocities.
We are specifically interested in...
So, its better to let software do endianess transformations at the endpoints... Using bridges in the middle of different endianess devices which do all the transformations, or having
dedicated hardware at the peripherals to transform representations have not so much value. Right? I ask all of...
There are no specific details right now, as the system's architecture is still
under development. There is a set of transaction level accurate processors,
an abstract Bus and the peripherals are sets of C-threads. The constraints
are that processors are Big-Endian and peripherals are little...
Hi all,
lets suppose that in a system, a Big-Endian Processor communicates with a Little-Endian Peripheral.
Which is the best practice to perform the endianess transformation? (processor transforms its big endian
words to little endian ones, a bridge in the middle of the communication path...
Nowdays control systems have many FSMs and each FSM has many inputs and many outputs. The transition and output functions you used to optimize with K-maps are
far too complex to be optimized this way. Nowdays each function is a multilevel gate network and not just a two-level AND-OR circuit with...
I disagree with a lot of simplistic opinions which mislead the designers.
In order to get the gains of an FSM-oriented synthesis flow you must know
at design time the exact states and exact transitions between states. Otherwise
the tool will produce a sub-optimal circuit.
Lets see DC' s...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.