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Here's a visual description of what I'm trying to figure out. Again, there are 2 controllers, the connections of which may be input, may be output at any given moment, but we are guaranteed never to have both controllers talking at the same time (exclusivity between controllers). The line to...
Correct, that's exactly what I need to do. The question is how is this done. My initial hypothesis is that this is not possible in VHDL when you want to do it with PORTs of type INOUT.
I have the following scenario:
I have a single device that I want to control with 2 different controllers. Only one controller will have access to the device at any given moment. This device uses SPI. That is the basis and general statement of my problem.
My real problem is this...SPI uses...
lan91c111 registers
I ended up getting the initialization of the part working and have it setup to auto-negotiate. There were a few problems, one being endianness. I am able to transmit packets, but am finding that there are "jumbled" packets being sent out in between good packets. I'm not...
I've been using signaltap, which is altera's embedded signal "scope" to look at signals. I agree with you that it's not obvious, but if the spec is accurate (which I've already found slight discrepancies between spec and driver c code) it shouldn't be crazy. I'll continue to look at the driver...
lan91c111
I am attempting a full VHDL based driver for the lan91c111 part. I've gotten pretty far along and have written a state machine to read/write registers. As I progress through the initialization requirements of the part, I realized that I have to "emulate" SPI through a register (Bank...
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