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Re: what delay statement won't be ignored for synthesis ? an
A delay statement cannot be used for synthesis because it uses gate/propogation delay to create the time delay and the number of gates can get large.
It will simulate fine though.
Re: 4-bit counter
I don't know verilog but asynchronous counter using JK FF shouldn't be too hard.
Use 4 JK FF, all inputs 1.
Clk0 <= Clock
Clk1 <= Q0
Clk2 <= Q1
Clk3 <= Q2
Broadly speaking, I would think it was an extra addition to the circuit which would reduce any variation in the output due to changes in internal/external parameters
e.g. a temperature compensated circuit.
What are you working on?
Hiya all,
I am a newbie (both here and to analog ic design). I ve been working on Digital design for a few years now and i only got interested in Analog for my Masters.
I would appreciate it if you would post what circuits (basic and advanced) you most often design...
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