Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Re: LEC?
Post sim cannot be replaced by LEC...Post sim is a dynamic testing which ur functional paths are tested.. LEC just checks the proper values are passing in by comparing RTL with netlist or netlist with netlist...
Post sim with SDF annotation is to check for timing with the...
lec sample script
Hi Arthur,
LEC is nothing but Logic Equivalence checking.. LEC can be done with Conformal, Formality, Formal PRo tools..
It is basically checking functionality between RTL and Netlist... and also you can check the functionality between pre-layout netlist and post layout...
Deepa,
When doing EM analysis in Magma, the report clearly shows the hotspots where the EM violations are. if you go through the report properly it even says that what is the actual current density and required density. It also gives suggestion on adding vias or increasing the width of metal...
Re: what is delay cell ?
As the name says delay cells provide more delays in the order of ns in some libraries.
functionality is same as buffer. These are basically used for hold fixing if the violations are more.
Please guard band this cell with normal buffer as this might give a transition or...
Re: L-shape floorplan
Hi ,
I dont have idea abt the tools u have specified, but in MAGMA I can give u the ste of commands,
create polygon <name>
polygon add name <x , y, w, h>
polygon add name <x , y , w ,h>
create polygon < name_inner>
polygon copy <name_inner> <name>
polygon shrink...
Flop cloning in Magma
Hi all,
Is it possible to clone flip flops in MAGMA.
If possible can anyone list out the commands for the following.
Thanks and Regards,
Pinkesh
Thanks Thomson,
But the think is according to the architecture the rtl pepole says that the path will be big as logic levels cannot be reduced.
I m using MAGMA as optimization tool.
The commands which u have given, I m not aware as I have not worked on Synopsys tools.
Is it possible to clone...
Physical design refers to making layout for the design. This can include Full Custom (Layout for each transistor is made by hand) or semi-custom(Layout is automatically generated by a P&R tool from a netlist).
Physical Verification Refers to verifcation includes following two major two steps...
set_critical_range, synopsys
Hi all,
How do i reduce the delay from 1st flip flop to the logic. I am having a delay of 1.5n before reaching to a logic bcoz of which my slack is getting worst.
How do i optimize.
Buffering has made a delay worst as it a very datapath oriented block and with a...
Re: tcl/tk
Hi,
Specify what u want properly.There is nolink bet VHDL and TCL.
If u want to learn TCL take this document this will help u out.
Rgards,
Pinkesh
Hi,
I dont know abt the equations on how much Decap cells are required if chip is consuming 10W of power.
Thinking of Decap is useless as ur chip is consuming 10W of power as that wouldnt help.
Please do check ur design and how much power is consumed by memoreis.
Also is u want to out decap...
Re: Project ideas for VLSI tsmc.18micron for a group of 4 pe
Hi,
Canu please be specific on what domain u want to do ur project,
DSP ,
wireless networking,
multimedia processor etc..........
Pinkesh
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
