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Hi Bigdog
"the external clock input is divided by the asynchronous ripple-counter prescaller so that the prescaller output is symmetrical"
I found above sentence in the PIC mid range Manual, so I would like know that what is the capability that ripple counter has to capture clocks at 20ns delay...
hI Bigdog
As per your reply in post#4
0.5(1us) +20ns = 520ns minimum pulse width
This is the Maximum frequency Timer0 can capture 1/1040ns , I think in other word the Timer0 takes 1040ns time to capture single pulse of it's maximum frequency
hi
as per data sheet
External Clock Synchronization
When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is accomplished by sampling the prescaler
output on the Q2 and Q4 cycles of the internal phase...
Hi
Please look at the attachment
As per the figure in the T0CKI High Pulse Width it takes No (Prescaler 0.5TCY + 20) times
that mean to capture the High Pulse Width of external clock, the MCU takes 0.5TCY + 20 times
This is related to pic16f877a
It would be much appreciated any one can...
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