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Hi Chunlee, Welcome to RFIC field. This forum is a very good forum. I leraned much from it. Also we can help each other from this forum. For hspice, I am not skilled in it. The manual is always the best teacher for EDA tools. However, if have problem in the design, it is aleays my pleasure to...
Hi Chunlee,
The gain is S21 or S12, it is depend on which terminal is input (it is not a problem, am I right? :-) ) . For the power gain, as we know, power=sqr(voltage)/impedance. So you can refer to this to calculate the power gain for different output impedance. During simulation, if your...
Hi Willem,
I just want to know the Q you mentioned is for which network. As we know for L network, the Q is fixed by the input resistance and output resistance. Since you want to match 2.3 ohm to 3.3 -j 3.94, you should include the -j3.94 to your network first, so the matching is from 2.3 to...
Hi Chunlee, I think for common gate LNA, the gate is a good AC ground, so in theory, Cgd is no effect on input. I think since you match input to 50 Ohm, your Gm is about 20 mS. Draw the small signal circuit of common gate LNA, the drain voltage affect the ids, ids affect Vgs. You can perform a...
moscap
if you want to use a normal NMOS as the varactor, you can connect the source and drain together in layout as you said. In fact, MOSCAP is a three terminals device, the gate, the source/drain and the p-sub. Normally the gate voltage is fixed the tuning voltage is applied to source/drain...
A-Mode Varactor is a NMOS in N-Well, Normal NMOS is a NMOS in P-Sub. The difference is for A-Mode varactor, the channel is already N- dopped. As we know Normal NMOS varactor, sweep Vgd from neg to pos value, it goes through A -> D -> I states. For A-Mode, it is D -> A (Since the channel is...
Bias the MOSFET use DC voltage source as you want, remember to insert a large inductor between the DC voltage source and your drain, gate, source etc. After this, connect a 1V AC source to the gate, perform a AC simulation on the frequency range you care, then plot out the current flow through...
It is hard to say the exact value. It depends on the substrate conductivity, the ploy doping, the oxide quality and height. You can refer to some semiconductor physics books or some bsim3 model file to get an idea. Thanks.
There is a good sample uder the cadence installation directory/tools/dfII/rfLib, you can read the SpectreRF user guide first. This user guide discuss how to use Spectre/SpectreRF to simulate RF circuit and system in detail, there is also an example for behavioral simulation for PLL, with Verilog...
i need tsmc .25um @DS design kit (i have all the models)
I don't have the design kit. but I have an idea for you, why not build a design kit by youself since you already had the model, you can refer to ADS manual to build your own design kit. There is a sample work under ADS examples, you need...
VCO starting constrain
I think it is necessary to keep the safety factor, to increase safety factor, you can increase W/L, if increase W can cause the problem you said, then you can reduce L. Also LC tank is a key in VCO. The Q has effect on safety factor also. If the safety factor is low, the...
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