Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
>> agree, GLS with SDF!
>> GLS w/o SDF can do to find out unreset flops that causing problems, but hard to tell it can find all!
>> use CDC (clock domain crossing) check in formal tool instead??
>> fine!
'synchronization flop' is ambiguous, i thought you were mentioning all DFF w/o async set/reset...
So, I think the following page might be useful. It intends to disable timing check on specific instance selectively and could be a solution for u:
Disable timing check selectively
And pls wait...
I'm not familiar with vcs. But i would probably **** into the standard cell that used, and comment out $setup, $hold etc lines within specify block of Flop models under concern.
- phixcoco
kyonglee,
(1) Follow kornukhin's instruction by turning off time violation check first, X from timing violate cells will disappear. But in 4-state simulation, it's a large chance, you'll still meet X during gate-level simulation. They are rooted in uninitialized registers or mems, some may...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
