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what a coincidence. I read a book yesterday. it has some chapters focus on low power flip flop, such as double edge trigger, low input cap on clock signal, and etc. It's name is "Low power CMOS Circuits technology: Logic Design and CAD Tools".
there are several low power optimization strategies...
Re: Multi-Clock Problem
Thank you Advares.
I think the solution with PLL/DLL is far too complicated for our design (about 10k gates). But I will keep the mesochronous solution in mind.
Re: Multi-Clock Problem
Thank you kbulusu.
I have to say we haven't gone that far in our next version. I think you are right. We need more information to determine the real problems. I just want to reduce the risk beforehand.
Re: Multi-Clock Problem
Thank you FvM.
Yeah, the delay is what we really concerned about now.
I'm sorry that I forgot to say we will insert clock gating cells in the tree. and to achieve as low power and area consumption as possible, we attempt to insert them manually to the root of clock...
Multi-Clock Problem
In our design, we have to use multiple clocks with different frequency. But these clocks are generated from one clock source.
Technically, this is not multi-clock-domain problem. So inter-block signals are not that hard to design.
But in the back-end flow, we encountered...
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