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pgadde1

Recent content by pgadde1

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How does inout pin declaration in VHDL work?

I wonder why everybody left vhdl!! Thankyou so much for your time. QUOTE=mrflibble;1119901]I doubt the inout is going to work that way... My vhdl skill is virtually non-existent so I´d better give you a random link: http://www.altera.com/support/examples/vhdl/v_bidir.html And then in your...
- pgadde1
- Post #19
- Aug 4, 2012
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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How does inout pin declaration in VHDL work?

Yeah u are right am trying to intialize inout pins the same way as in pins in both .vhdl and test bench but its showing UUUU. Syntax am using Sel inout std_logic_vectors := "00"
- pgadde1
- Post #17
- Aug 4, 2012
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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How does inout pin declaration in VHDL work?

Re: vhdl inout pins Hi am trying to do something similar here in vhdl I am taking a output from a component and its giving me the correct output But when I try to feedback it it back to the input its not working. EX: input in std_logic_vector = "1110" ---some constnt value sel : inout...
- pgadde1
- Post #15
- Aug 4, 2012
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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Help on VHDL design of counter using LUT of FPGA

Thankyou :)
- pgadde1
- Post #15
- Aug 4, 2012
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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Help on VHDL design of counter using LUT of FPGA

I am not aware of this concept of using carry chains in a CLB and programming in vhdl. I 'll start looking in that direction. Thanks - - - Updated - - - Yeah I was given a project, asked me to develop a Test pattern gernerator(up down binarycounter ) which uses a CLB in FPGA in VHDL . So I...
- pgadde1
- Post #13
- Aug 4, 2012
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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Help on VHDL design of counter using LUT of FPGA

I need to build a updown counter using a CLB in virtex -4 FPGA. I can only use components inside it i.e. LUT. So I need to bulid a 4bit binary up down counter using LUTs
- pgadde1
- Post #9
- Aug 4, 2012
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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Help on VHDL design of counter using LUT of FPGA

Thanks for the replies. I had to build a pattern generator/updown counter using LUTs. I dont know how to do this because it has 4 inputs and one output and I need a 4 bit up down binary counter .so thats why am using LUT's 16:1 mux . Could you please let me know how to achieve it using...
- pgadde1
- Post #7
- Aug 3, 2012
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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Help on VHDL design of counter using LUT of FPGA

Thanks for the reply vipin. But I need to use components in virtex4 fpga and build a up down counter. so I need to use a 16:1 mux and a D FF (D FF if needed). But in the link there are gates I need it with a 16:1 mux. So any help in this direction is really helpful.
- pgadde1
- Post #4
- Aug 3, 2012
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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Help on VHDL design of counter using LUT of FPGA

hi, I am facing the similar problem. Please let me know if u find a solution for it
- pgadde1
- Post #2
- Jul 18, 2012
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design

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pgadde1

Welcome to EDAboard.com

Recent content by pgadde1

How does inout pin declaration in VHDL work?

How does inout pin declaration in VHDL work?

How does inout pin declaration in VHDL work?

Help on VHDL design of counter using LUT of FPGA

Help on VHDL design of counter using LUT of FPGA

Help on VHDL design of counter using LUT of FPGA

Help on VHDL design of counter using LUT of FPGA

Help on VHDL design of counter using LUT of FPGA

Help on VHDL design of counter using LUT of FPGA

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