Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by pfaes

  1. P

    Is there a HDL Code browser?

    Sigasi has a free Starter Edition of its VHDL code comprehension tool. Works much like Eclipse. Features include: navigate to declaration, hover to see declaration, etc. **broken link removed** Philippe Sigasi founder
  2. P

    Delay before assignment.

    Don't trigger on a rising edge of "fire", that way, you would use "fire" as a new clock, instead of a control signal. Instead, check for the old value and compare to the new value. Then start counting 4 clock cycles. Counting 4 clock cycles can be done by shifting the values in a shift...
  3. P

    Delay before assignment.

    In simulation, you can delay a signal assignment using after, but that is probably not what you want: **broken link removed** You probably need to create a signal that knows when the junk has flushed through your module, and use that to switch the output on or off. I propose you add something...
  4. P

    can we make FPGA kit ourself

    I also bought the BeMicro SDK last week. Nice and cheap development board. I'd strongly advice buying one instead of building one yourself. Philippe

Part and Inventory Search

Back
Top