Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hey, I'm new to Quartus and I need to draw a schematic for the following Verilog code for an adder:
module adder#(parameter W = 8)
(
input clk,
input [W-1:0] a_i, b_i,
output [W:0] sum_o,
output is_odd_o
);
reg [W-1:0] a_r, b_r;
reg [W:0] sum_r;
reg is_odd_r;
wire...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
