Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
double clock frequency
Can I suggest using an analogue component (from mini circuits or equivalent).
If jitter is a problem. FPGA/CPLD will probably introduce a lot more jitter as they are effectively a digital component. I believe DCM and PLL have to add jitter for them to even work. But you...
xilinx tig constraint clock errors
I agree with with yx.yang the design need to handel the asyncronise signals. But you at least still should tell the Map/ Place and rount tool not to worry about them using (TIG) If they are flaging a timing error.
Is the skew come from outside or inside the...
aes fpga
May I sugest you program up a COM port (in JAVA or C) instead of using Hyperterminal (a real pain the the arss to do anything cleaver with - you'll save a lot of time in the long run).
(COM port use RS232 look the standard up
- you may need to do voltage conversion with a chip if it's...
First thing is to find out what pins connect to what in your data sheet eg(A2, AF12 etc)
Make code in ISE to connect switches or buttons to LEDs. Comile your into a bitstreem (using ISE) program into your device (using IMPACT) and check the code does what you expected it to do.
There is rather...
Re: Xilinx 92i env variables
Sorry I cannot tell you the enviromental variables for ISE 9.2i.
Re installing should fix this for you? Or have you already tried this?
xilinx ise tnm tnm_net
BUFR is a regional clock buffer. Use on clock capabile inputs not global clock inputs.
The tool cannot calcluate timing for FFs that cross clock domains unless you specify that the clock are dependent.(if your using Xilinx ISE look into using TNM_NET / TNM).
Note: if...
Re: Capturing Pulse
If there is no phase relationship between the clock domains then metastability is always a problem that needs to be dealt with. Or else your code will all of sudden mysterious stop working until you reprogram it.
One way to deal with metastability is to make sure that all...
Re: Capturing Pulse
Fist of all metastability could be your problem. The recive filpflops could be getting stuck in a meta stable state. However if this is your problem then it should work sometimes just not all the time.
To remove metastability problems (well reduce them down to somthing like...
masking vhdl
This is how you do it.
input and output are signals of the same length.
process(clk)
variable leading_zeros: boolean;
begin
if rising_edge(clk) then
for a in input'high dowoto input'low loop
leading_zeros := true;
if input(a) = '0' and leading_zeros then...
Re: state machine error
All state need to be unique (not sure I understand the question). How you encode the state does not matter as the sythesis tool will re-incoded them to as is sees fit anyway.
Try to use names to encode your state (easier to read - I don't know how to do this with Verilog).
how to provide delay by using counters
My apolgies I don't realy understand the question.
However in my when it comes to state machins it's best to have at least two processes a a syncrnoise one and an ansyncronise one.
The ansyncronise process is dependent on (signals in the senstivitly...
state machines with counters
You need make signals (as needed) like:
load counter enable,
load counter value,
counter incerment enable,
etc...
These signals talk from your anysrnconouse process to your syncronouse (state advance) one.
You could also put the conter into it's own process...
error vhdl infix operator
I beleave your problem is the + operator does not understand one or two of the types coming into it and/or out of it.
Try converting all the + operator inputs to integers and back again like so:
f0 <= conv_std_logic_vector(conv_integer(seq_pat(0) xnor...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
