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yes by LVS BOX statement in calibre , but it just doesn't work ( i don't know why) , the extracted netlist from layout ignores the cells stated as black boxes !! an incomplete extracted netlist and useless LVS :( !!!
Added after 5 minutes:
hi :)
thx for your answer ... but in the encounter ...
you can not just ignore these lines in the rule file , they are necessary to define how can calibre read the port names .
what these lines do ?
define a text layer which is 137 to read from it general labels , and attach this layer to the metal1 layer
when a label is there in layer 137 , and...
hi
i have the same problem with calibre ....
i've used the LVS BOX statement
but same errors and wornings
i've the gds out of the encounter
and the verilog file also out of the encounter
the calibre v2lvs translates my verilog into spice using the verilog libraries..
the source netlist in...
hi
i'm in an asic project .
we use tsmc 090 standard cells.
we generated rams using artisan !
we use synopsys design compiler (synthesis)
first encounter(layout)
calibre(lvs , drc etc)
to perform post layout simulation on modelsim , and verilog to spice netlist translation using calibre v2lvs...
hi :)
in the asic design flow using standard cells supplied from he foundry , can i see the contents of the cells ? in calibre DESIGNrev ? can i run LVS and identify the devices ?
the layout generated from the first encounter doesn't contain any poly !!! how can i identify the cells?
hi :)
about the process of the tsmc090
what is the DNW layer (layer no.3)?
where is the active layer ?
i want to know these informations to be able to write the calibre lvs rule file defining the devices !!!
thx :):?:
hi :)
i use calibre DESIGNrev to open a layout generated by candece first encounter .
in cadence first encounter : i use a map file when streaming out a gds2 layout.
when i open in calibre i see those layers , example :
31
31.1
33
33.1
etc....
what is the difference between layer number 31 and...
hi
i'm in an ASIC design project .
synthesis is done by synopsys design compiler .
placement and routing by first encounter.
we use standard cells of tsmc 90nm
calibre is used for verification (DRC/LVS/PEX)
when i try to run LVS : it flags this error
error:no module for cell <cell_name>...
hi :)
i'm using calibre to perform drc / lvs , i don't have the rules file , so i'm writing it , i'm asking about the dimensions , i read the rules fil of the 45 nm , the units are not clear , it doesn't define the units used ( um or nm or what ?) , an example of he rules wriiten :
" internal...
hi :)
i'm new to the IC verification tools .
i uploaded the tar archive , i extracted it , but i can not understand how to use it ! can u help me plz ? :?:
thank u :)
Added after 8 seconds:
hi :)
i'm new to the IC verification tools .
i uploaded the tar archive , i extracted it , but i can...
hi :)
i'm new to the caliber verification tool ( and to the ic physical verification)
i have this error when trying to run calibre -gui
// Encountered Licensing problem:
// calinteractive
// License request for calinteractive feature failed
// Error: Calibre Exiting due to licensing...
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