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When I cast the command 'report_disable_timing' with dc_shell, what is the difference between the different flags:
c case-analysis
C Conditional arc
l loop breaking
u user-defined
L stored loop breaking
What do they actually mean, precisely?
I know that 'l' (loop braking) means that there...
I am using IC Compiler to generate the layout of different blocks, in order to import them in a higher level module.
But when I import the Macros I generate in the toplevel module, these do not have the Power and Ground pins, and when I synthesize the pg rail, I get the following error:
Error...
Hi,
I am not an expert, but as far as I know, clock tree synthesis is performed during place & route of a design. It is a step that introduces wires dedicated to clock distribution, as well as buffers (repeaters) to speed up the signal propagation.
I know there are some different topology for...
Dear all,
I am trying to place & route a design using synopsys icc.
This design is a composition of sub-blocks, that I already placed and routed.
How can I import these blocks inside my toplevel, so that I do not have to re-run all the p&r steps, but just perform a merging operation (and final...
I think the only way you have to resolve this is to add a "dummy" inverter to your library, so that this is accepted from the synthesis tool.
Then you put a "set_dont_use" on this cell, so it will not be inserted in you final design.
See if this works...
Hi all,
I am trying to synthesize an asynchronous block with Synopsys Design Compiler.
My design is correctly elaborated by the tool, but when compiling it "optimizes" the architecture modifying the netlist.
For instance a XOR2 can be transformed in AND + OR gates, or multiple gates can be...
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