Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
minimize floor plan area
Thanks raki123
Added after 10 minutes:
Raki31
In case of power planing for a block,how we decide the width of power rings(metal widths for vdd,vss) and straps and how to calculate how many vertical/horizontal straps are needed for a block.
If you have any document...
synopsys icc flow
Thanks raki31.
It means, pin locations are depends on the other hierarchical blocks, not on the std cells/macros placement of the block that we do floorplan
synopsys icc user guide
Thanks raki
Regarding 2nd question i may not be able explain better way, but let me put here sequence of commands that i use to do block level floor plan
# read verilognetlist
1)read_verilog
# pin constraints
2)read_io_constraints<tdffile>
# timing constraints...
Hi,
I am newly learning pd using synopsys ICC flow, pls help me in understanding more about following questions
While doing the block level floor plan,
1 How we decide the size and shape of the block.which factors we have to consider to decide the size and shape of the block
2 reading the...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
