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pavan.ps

Recent content by pavan.ps

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How to pass data b/w Synchronous Domains

Sample the data with the negedge of high sync clk and use it with the low sync clk Data rate should be compatible with low sync clk.
- pavan.ps
- Post #6
- Jul 23, 2010
- Forum: ASIC Design Methodologies and Tools (Digital)
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frequency divider by 2 in Verilog?

always@(posedge clk or negedge rst) if(rst) q<= '0'; else q<= ~q;
- pavan.ps
- Post #3
- Apr 16, 2010
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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Digital to Analog conversion

the code provided by you gives only digital output. DAC_OUT(8-bit). If u need the analog signal, u need to feed this digital output to a digital-to-analog converter to give analog signal. So, If u hav a 8-bit signal, interface the FPGA to DAC such that you get the analog output. Hope this helps..
- pavan.ps
- Post #2
- Mar 31, 2010
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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Verilog how to lock value?

Can you tell the clock u use to generate the A signal? Say, if u generate the A signal with a lesser clock than clk then counter increments many times.
- pavan.ps
- Post #2
- Mar 31, 2010
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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What is an easy way to multiply a binary number by 255?

Re: Help Required! x*255 = x*256 - x*1 = Shift by 8 - x Hope this helps..
- pavan.ps
- Post #2
- Mar 31, 2010
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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How can I implement a 4-variable function using 4-to-1 mux?

Re: How can I implement a 4-variable function using 4-to-1 m You can find the solution for function implementation using multiplexers in morrismano. Chapter 5 and page 179.
- pavan.ps
- Post #5
- Mar 29, 2010
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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modelsim 6.2g - looking inside RAM

Re: hekp with RAM In the modelsim window, Under workspace Tab , click on the sim tab and the find the instance of the RAM. Right-click on the instance and select "add to wave."
- pavan.ps
- Post #2
- Oct 29, 2008
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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Error in textio read when simulating a testbench in Modelsim

Re: About textio read? i doesnt find any error.. So, check the declarations and the type of data in the .txt file
- pavan.ps
- Post #2
- Oct 22, 2008
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design
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verilog to vhdl translation 1

Hi.. Go thru this piece of code VHDL. if(wb_i_adr[31 downto 30] = "11") then sel_ram <= op; elsif(wb_i_adr[31 downto 30] = "00") then sel_rom <= op; elsif(wb_i_adr[31 downto 30] = "01") then sel_io <= op; end if;
- pavan.ps
- Post #2
- Oct 22, 2008
- Forum: PLD, SPLD, GAL, CPLD, FPGA Design

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pavan.ps

Welcome to EDAboard.com

Recent content by pavan.ps

How to pass data b/w Synchronous Domains

frequency divider by 2 in Verilog?

Digital to Analog conversion

Verilog how to lock value?

What is an easy way to multiply a binary number by 255?

How can I implement a 4-variable function using 4-to-1 mux?

modelsim 6.2g - looking inside RAM

Error in textio read when simulating a testbench in Modelsim

verilog to vhdl translation 1

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