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Thank you for patiently replying to my inquiry. I tried to use Verilog instead of VerilogA in Cadence but I am experiencing the error below upon saving and checking the codes.
There is still an error on the always statement after adding ":" after the default.
// VerilogA for BGR_v2, decoder2, veriloga
`include "constants.vams"
`include "disciplines.vams"
module decoder2 (
binary_in , // 4 bit binary input
decoder_out, // 11-bit out
enable // enable for the...
Thankyou Sir/Ma'am but we get rid of the ';' and there's still an error or marker on the always statement. The marker message says "Error:syntax error."
Hi friends! I'm a student and I'm having difficulty with my codes on our 4 to 11 Decoder. This is done in VerilogA code on Cadence. I've experienced this error and dunno what's the problem. Can someone help me fix my codes? Thankyou :)
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