Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by paradbird

  1. P

    look at my vhdl, why it doesn't work after synthesis

    I want to do asynchronism write, but this program can't work after synthesis, I don't know why. Please give me some advise. Thanks a lot. library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity ioInput is port( D_out1 : out std_logic_vector(255...
  2. P

    What does #iteration limit reached mean in Modelsim?

    I always meet this error when I simulate in modelsim: # Iteration limit reached. Possible zero delay oscillation. See the manual. what this mean and how can I do ? Thanks.

Part and Inventory Search

Back
Top