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Thanks both for the feedback. I analyzed this further and I think they are the HIGH and LOW driver signals.
When both are LOW the gate seems to output HIGH, and when both go HIGH the gate outputs a LOW. In addition, when the signals opposite each other the gate seems to go into input mode...
Dear forum members,
I'm currently studying an old early 90s IC and curious about the structure of the data pad below. I know the right most line is an input but I have no idea what the other two connections are for?
Any ideas/comments appreciated.
Hi forum!
Just got my hands on this Japanese power supply thinking that it had an internal switch able to select 110 vs 220. Sadly it doesn't but apparently other versions of the power supply do have it.
After inspecting the pcb I have found that indeed does have a place for the switch but...
@SunnySkyguy thanks for the feedback, that actually helped me looking at it with different eyes. It happens that this design requires a certain initialization: "data" and "a" need to be low when the clock begins, then "a" needs to go high in order for it to work.
After doing so the register...
Hi again dear forum members,
Here's another CMOS challenge that I wanted to share with you. I have been fighting for a while with reverse engineering this cell register (presumed register) and haven't managed to get it to work correctly under irsim, if my understanding is correct this should...
Hi Dick, thanks for your input, that was a great tip. Just found **broken link removed** online showing a standard cell nmos decoupling capacitor. While the cell is almost identical, it puzzles me the fact that the poly on my cell does not cross the ndiff completely. Any thoughts on that?
Dear forum members,
I've been working for a while in the reverse engineering of an old IC, just a hobbyist project (im not an electical engineer).
There's one component in the circuit that I havent been able to figure out its function yet so i'm reaching out to you guys for help.
Below you...
Hi there, i'm new to this world and currently playing around with magic and irsim to understand how vsli cells work.
I'm wondering if anyone can give me a hand to understand how to represent what this 3-input gate below, i'm failing to understand how to representing in boolean or what...
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