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Thank you Hairo.
the site you referred is based on Verilog and I am using VHDL. Still I got an idea.
I am a very novice in VHDL programming. I want to display a bit-stream (for example: 1101) in the LCD of Xilinx® Virtex™-4 LX MB Development Kit. For the time being I take the inputs (EN, RS...
Hello
Good Day.
I want to display a bit-stream (for example: 01001101) in the LCD of Xilinx Virtex™-4 LX MB Development Kit. Can anyone tell me how can I get example VHDL code to display bits on LCD?
Best regards and thanks in advance
pantho
needs help on CLOCK
Hello everyone,
Good Day.
I want to download the following VHDL code to FPGA Xilinx Virtex-4.
process(clk)
begin
if (clk'event and clk = '1') then
if (cycle = '0') then
x <= a;
cycle <= '1';
else
x <= b;
cycle <= '0';
end if;
end if;
end process;
I have...
Hello,
I am using Xilinx Virtex-4 LX MB Development Kit, FPGA is Virtex-4 xc4vlx60-ffg668. Can you plz tell me how i get the example ucf for the board?
Thanks in advance
pantho
how to program virtex 4?
Hello,
I want to download a simple VHDL program to FPGA Xilinx Virtex-4. I am using ISE 10.1 and iMPACT 10.1. the code is very simple. it is an AND gate that works at clock high
------------------------------
process(clk)
begin
if (clk'event and clk = '1') then
y...
Hello everyone,
I am very new in VHDL programming. For my work I am using ISE 10.1 and ModelSim XE III 6.3c. I am facing some problems in programming a simple code. the code is as follows:
------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use...
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